The present invention relates generally to power and power-density management in electronic systems for testing digital logic circuits. More particularly, the subject invention pertains to a method and apparatus for reducing power dissipation during a scan operation during testing of digital logic circuits which provides for scanning data while switching a limited number of nodes during scan-in and scan-out of input and result chains, and which isolates the logic circuit from random stimulation by scan chains as they are scanned.
As the complexity of today's circuits limits the practicability of sequential test generation to small circuits only, scan testing has been commonly used to ensure easy diagnosis and test generation times within practical limits.
While scan testing helps keep test generation times within limits, the large number of scan cells and patterns generated, as a result, increase the test data volume and the tester time requirements inordinately. The increases in turn boost test application cost by necessitating prolonged utilization of increasingly expensive testers.
As the sizes of the circuits increase, the pin to gate ratio reduces. Since the number of scan chains, which is limited by the number of I/O pins, cannot increase, the number of cells per scan chain has to increase, which directly affects test time.
Test time directly impacts the chip cost and hence it is of paramount importance to reduce test time. Two options are open to reduce the time used for scan testing:                the volume of data processed with scan testing can be reduced, or        the speed with which processing occurs can be increased.        
A number of schemes have been proposed for test data volume reduction of scan-based deterministic testing by improving the effectiveness of test compaction and compression schemes. While compaction schemes try to reduce the number of patterns generated without compromising fault coverage levels, compression schemes in turn target reduction of the storage requirements of the compacted test patterns. Additionally, shifting the decompression task to the circuit under test reduces test application times. A description of one test volume reduction scheme, as well as references to additional such schemes can be found in Ismet Bayraktaroglu and Alex Orailoglu, “Test Volume and Application Time Reduction Through scan Chain Concealment”, Design Automation Conference 2001.
Traditionally, scan testing has occurred at speeds well below the nominal operating frequency. One reason for this lower operating frequency during scan testing has been the potential for chip damage due to excessive power dissipation. Power dissipation is generated from two distinct aspects of the scan testing operation, (1) the need to switch all latches with highly random data which leads to higher switching activity than during normal operation, and (2) the stimulation of logic with the highly random activity during every cycle of the scanning process, leading to higher than normal glitch rates in the logic.